Wednesday, June 20, 2012: BRAUNSCHWEIG, GERMANY: Symtavision has announced that SymTA/S supports the timing design and verification of embedded software developed for the new multicore AURIX microcontroller family from Infineon Technologies.


Featuring up to three independent 32-bit TriCoreTM CPUs, the AURIX MCUs from Infineon have been designed to meet the exacting ISO 26262 safety requirements for automotive applications while significantly increasing performance. The modular design and memory approach of AURIX provide the scalability that customers increasingly demand and its in-built encryption technology is designed to meet the upcoming security requirements of next-generation vehicles.

The AURIX family is ideally suited to powertrain applications including hybrid and electric vehicles as well as safety applications such as steering, braking, airbag and advanced driver assistance (ADAS) systems. With AURIX, both powertrain and safety applications can be controlled using a single ECU.

As Symtavision's partner, Infineon recommends SymTA/S for model-based development of automotive ECU software for multicore systems. Multicore platforms offer new opportunities and advantages and also extend the design space for software architectures like runnable to core mappings. The decision as to which runnables should be mapped to which cores and which data containers lie in which memories, is strongly influenced by communication overheads.

Communication between the cores, realized through Inter OS-Application Communication in AUTOSAR 4, and also the communication with external memories can lead to significant additional execution times for runnables. These communication overheads can easily eat up the performance improvements expected from a multicore ECU. The question is: how big are these overheads and how can they be reduced? SymTA/S provides the answers, efficiently facilitating the memory mapping of runnables and data as well as answering any necessary 'what-if' questions.

This helps software designers to produce a software architecture of good quality and to utilize multicore platforms efficiently.